verilog_slides设计使用手册.pdf

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Overview of Verilog HDL Sunil Maloo October 14, 1998

Sunil Maloo Verilog Presentation 1 Verilog HDL What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simulation of designs ➥ Verilog is a discrete event time simulator What is VeriWell? ➥ VeriWell is a comprehensive implementation of Verilog HDL

Sunil Maloo Verilog Presentation 2 Program Structure in Verilog Verilog allows hierarchy in a design using modules and ports System ➣ System instantiates Module_1 and Module_2 Module_1 Module_2 ➣ Module_2 instantiates Sub_Mod Sub_Mod

Sunil Maloo Verilog Presentation 3 Modules Verilog language describes a digital system as a set of modules ➥

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